Wykaz publikacji wybranego autora

Robert Szczygieł, dr hab. inż., prof. AGH

profesor nadzwyczajny

Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
WEAIiIB-kmie, Katedra Metrologii i Elektroniki

  • 2023

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika, elektrotechnika i technologie kosmiczne

  • 2018

    [dyscyplina 1] dziedzina nauk inżynieryjno-technicznych / automatyka, elektronika i elektrotechnika

[poprzednia klasyfikacja] obszar nauk technicznych / dziedzina nauk technicznych / elektronika

Identyfikatory Autora Informacje o Autorze w systemach zewnętrznych

ORCID: 0000-0001-6342-0107 orcid iD

ResearcherID: B-5662-2011

Scopus: 6603163212

PBN: 5e70922c878c28a0473911fe

OPI Nauka Polska

System Informacyjny AGH (SkOs)

1
  • 23552-channel IC for single photon counting pixel detectors with 75 $\mu m$ pitch, ENC of 89 $e^{-}$ rms, 19 $e^{-}$ rms offset spread and 3\% rms gain spread
2
  • 32k channels readout IC for single photon counting detectors with 75 $\mu$ pitch, ENC of 123 $e^{-}$ rms, 9$e^{-}$ rms offset spread and 2\% rms gain spread
3
  • 3-D integrated 2 cm × 2 cm, 65k pixel X-ray detection module with through-silicon vias
4
  • 64 Channel acquisition system for recording biomedical signals
5
  • A bidirectional 64-channel neurochip for recording and stimulation neural network activity
6
  • A family of integrated circuits in submicron technology for in vivo and in vitro high density MEA experiments
7
  • A fast 300k X-ray camera with an energy window selection and continuous readout mode
8
  • A low noise, fast pixel readout IC working in single photon counting mode with energy window selection in 90 nm CMOS
9
  • A pixel readout chip designed in 90nm CMOS process for high count rate imaging systems
10
  • A pixel readout chip in 40 nm CMOS process for high count rate imaging systems with minimization of charge sharing effects
11
  • A prototype chip for pixel hybrid detector in 90 nm CMOS technology
12
  • ADCs in deep submicron technologies for ASICs of pixel architecture
13
  • An intensive mixed-mode ASIC design course for summer student practice
14
  • Analog pixel front-end for VIPIC-large detector
15
  • Analogue multiplexer for neural application in 180 nm CMOS technology
16
  • Analysis of full charge reconstruction algorithms for X-ray pixelated detectors
17
  • ANN on-chip and in-pixel implementation towards pulse amplitude measurement
18
  • Area efficient low power neural amplifiers using MOS and MIM capacitors in submicron technologies for ultra low corner frequencies
19
  • ASICs in nanometer and 3D technologies for readout of hybrid pixel detectors
20
  • Characterization of a photon counting CHASE Jr. chip in a 40nm CMOS process with the C8P1 charge sharing correction algorithm using a collimated X-ray beam
21
  • Charge sensitive amplifier for nanoseconds pulse processing time in CMOS 40 nm technology
22
  • Charge sharing measurements for digital algorithms achieving subpixel resolution in hybrid pixel detectors
23
  • Comparision of two different architectures of multichannel readout ASICs for neurobiological experiments
24
  • Comparison of two pole-zero cancellation circuits for fast charge sensitive amplifier in CMOS technology
25
  • DEDIX – development of fully integrated multichannel ASIC for high count rate digital X-ray imaging systems