Wykaz publikacji wybranego autora

Adam Gołda, dr inż.

adiunkt

Wydział Informatyki, Elektroniki i Telekomunikacji
WIEiT-ke, *Katedra Elektroniki

Identyfikatory Autora Informacje o Autorze w systemach zewnętrznych

ORCID: brak

ResearcherID: C-2122-2013

Scopus: brak

OPI Nauka Polska

1
  • A charge pump integrated in 180nm CMOS technology for voltage conversion in heat energy harvesters
2
  • A charge pump with power-on reset circuit
3
  • A set of temperature sensors and maximum temperature selection circuit
4
  • Analysis and design of PTAT temperature sensor in digital CMOS VLSI circuits
5
  • Analysis and verification of integrated circuit thermal parameters
6
  • Analysis of parameter-based temperature-controlled oscillator dedicated to method of optimum control of throughput
7
  • Analysis of steady state temperature distribution in CMOS integrated circuits
8
  • ASIC for investigations into thermal aspects in CMOS integrated circuits
9
  • ASIC implementation of high efficiency 8-bit 'OctaLynx' RISC microprocessor
10
  • ASIC implementation of high efficiency 8-bit “OctaLynx” RISC microprocessor
11
  • Asynchronous 4-bit flash analog-to-digital CMOS converter with over- and underflow detection system
12
  • Design and testing of CMOS asynchronous flash analog-to-digital converter
13
  • Design and tests of CMOS phase locked-loop
14
  • Design of CMOS analog and digital phase-locked loops based on resonant VCO
15
  • Effective supervisors for predictive methods of dynamic power management
16
  • Embedded PTAT temperature sensor for CMOS VLSI circuits
17
  • Energy collected by MOSFET capacitance and its temperature dependence
18
  • Energy consumption by CMOS gates
19
  • Energy losses in digital CMOS integrated circuits: state-of-the-art and future trends
20
  • Experimental verification of energy losses in CMOS gates
21
  • FPGA implementation of 8-bit RISC microcontroller for embedded systems
22
  • Generator sygnału zerującego
23
  • Generator sygnału zerującego
24
  • Impact of gate load on other gates on CMOS logic networks
25
  • Investigation into temperature impact on quasi short-circuit energy losses in CMOS gates